Chip yield and die size

Why does making a chip slightly larger cut the share of working ones by far more than a little?

A design team wants a little more cache. The die grows by a tenth — a change you could not see without a microscope. The manufacturing group refuses, and not because the wafer costs a tenth more: they say good chips per wafer will fall by something nearer a third.

Nothing about the process changed. The same machines print the same features with the same care on the same silicon. So where does a disproportion like that come from?

Begin with what spoils a chip. A speck of dust lands during lithography, a particle falls in a deposition chamber, a crystal defect propagates. Each event is a point on the wafer, and the process does not know where you drew your die boundaries. So the natural model is: defects rain onto the wafer at some average rate per unit area, and a die dies if at least one lands inside it.

If that raining is random and independent, it is a Poisson process, and the chance of catching no defect is e raised to minus the expected number inside. Call the defect density D and the die area A; yield is e to the minus A times D.

The shape of the answer is already visible: yield falls exponentially in area, not in proportion to it. Take a mature process at 0.1 defects per square centimetre (recalled, order-of-magnitude; early in a node's life it is much worse). A 1 cm-squared die yields e to the minus 0.1, or 90.5 per cent; a 6 cm-squared die yields e to the minus 0.6, or 54.9 per cent — the coin-flip regime that makes big processors expensive.

But the question was about a small increase, so differentiate. Good dies per wafer is the number that fits, roughly wafer area over A, times the yield: N is proportional to (1/A) times e to the minus A times D. Take logarithms and differentiate, and the elasticity — percentage change in good dies per one per cent of area — is minus one, minus A times D.

That is the whole answer in one expression. The "minus one" is packing: bigger dies, fewer of them. The "minus A times D" is the yield penalty, and it grows with the die you already have. At A times D of 0.6 the elasticity is minus 1.6, so a tenth more area costs about 16 per cent of the good dies. At A times D of 3 — a large accelerator on an immature process — the elasticity is minus 4, and the same tenth costs about 40 per cent.

Now try to cheat the model. Split one 6 cm-squared die into four of 1.5 and connect them. Each yields e to the minus 0.15, or 86.1 per cent; all four good is 0.861 to the fourth, which is 54.9 per cent — exactly where we started. The exponential is memoryless in area, so cutting a design up buys nothing at all if you insist on four good ones from the same wafer and packaging is free. That negative result is the useful one: it says the real gain must come from not throwing away the good neighbours — a bad small die is discarded alone, and a good one matched with another from elsewhere.

Two folk accounts should go. The first is that a larger chip has more transistors and so more chances one is bad — directionally right, fatally imprecise. The scaling quantity is area, not device count; a large die of sparse analogue circuitry suffers the same penalty. And the relationship is exponential rather than proportional, so the folk version cannot produce the cliff at all. The second is that poor yields mean a sloppy process; the same defect density gives ninety per cent on a small die and five on a huge one, so a yield figure quoted without a die area says nothing.

Now let me falsify my own model. Pure Poisson assumes defects fall independently. They do not — they cluster, arriving in scratches, edge rings and particle showers. Clustering helps large dies, because more defects pile into dies already dead and the survivors are cleaner than independence predicts. Measured yields on very large dies are reliably better than e to the minus A times D, which is why the industry fits a negative-binomial form with a clustering parameter instead. My exponential is a pessimistic bound, and the elasticity overstates the penalty by an amount growing with die size. The qualitative claim — that the cost per per cent of area rises with the area already committed — survives clustering.

The falsification test the account does pass is the industry's own experiment: chiplets. If yield loss were about process quality rather than area-proportional random hits, disaggregating a design would change nothing. Instead, splitting large designs into small dies and assembling only the good ones is standard for exactly the largest parts, and worth doing despite real packaging cost. Redundancy says the same: spare memory rows recover dies precisely because a defect is a random point, not a systemic flaw.

Where this sits next to its neighbours: tolerance-stack-up.md is the closest relative — both are about randomness deciding whether a manufactured thing is acceptable — and they differ at how the randomness combines. Stack-up is additive: many small independent variations sum, and because they sum in quadrature, n equal tolerances give the square root of n rather than n. Yield is all-or-nothing: one hit anywhere kills the die, so losses compound multiplicatively into an exponential. bathtub-failure-curve.md shares the selection logic of a population containing a few born broken, but its variable is time; here screening is complete at test, and the variable is area.

The load-bearing claim is that killer defects are approximately random in position and independent of the design's boundaries. If a large share were systematic — clamped to wafer edges, or driven by lithographic hotspots at particular layout patterns — yield would be a property of where on the wafer and what you drew, and the area law, with it the elasticity argument, would not hold.